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  2. 難波 一輝

難波 一輝

ナンバ カズテル  (Kazuteru Namba)

基本情報

所属
千葉大学 大学院工学研究院 准教授
学位
博士(工学)(東京工業大学)
ORCID ID
 https://orcid.org/0000-0002-8316-7281
J-GLOBAL ID
200901051769488954
researchmap会員ID
5000048015
外部リンク
2002年東京工業大学博士課程修了, 博士(工学), 同年千葉大学工学部助手, 2007年同大学院融合科学研究科助教, 2012～13年米国ノースイースタン大学客員研究員, 2014年 同准教授, 2017年 同大学院工学研究院准教授 現職.

研究キーワード

 1

研究分野

 1

経歴

 2

学歴

 1

委員歴

 2

論文

 79
  • Hisato Kashihara, Josaphat Tetuko Sri Sumantyo, Yuta Izumi, Koichi Ito, Steven Gao, Kazuteru Namba
    IEEE Transactions on Antennas and Propagation 71(2) 1943-1948 2023年2月  
  • Hisato Kashihara, Koichi Ito, Josaphat Tetuko Sri Sumantyo, Steven Gao, Yuta Izumi, Kazuteru Namba
    APSAR 2023 - 2023 8th Asia-Pacific Conference on Synthetic Aperture Radar 2023年  
    In the realm of regional emergency observation and real-time, high-resolution data acquisition, there is a burgeoning interest in the development of UAV equipped with Synthetic Aperture Radar systems (UAV-SAR). However, a critical challenge lies in achieving a UAV-SAR system that meets criteria such as high resolution, lightweight design, minimized payload, power efficiency, operational viability at high altitudes, robustness in extreme environments, extended flight durations, and full polarimetric functionality.To address this challenge, our research group envisages the creation of an X-band circularly polarized UAV-SAR system, designed specifically for disaster management and environmental monitoring, leveraging the 25 kg payload capacity of the UAV platform. The effective functioning of the SAR system necessitates a broadband antenna with complete circular polarization capabilities to ensure precise observations. The antenna must also be compact, lightweight, possess high gain, accommodate broadband chirp pulse signals, and exhibit excellent antenna isolation and axial ratio (AR).To this end, we put forth a novel design featuring a 4×4 array antenna outfitted with axe-shaped radiating elements. The proposed antenna underwent rigorous simulation, fabrication, and assessment within an anechoic chamber. Additionally, an indoor polarimetric scattering SAR experiment was conducted employing canonical targets to assess the polarimetric SAR proficiency of the system equipped with the proposed antenna.
  • Keisuke Kozu, Yuya Tanabe, Masato Kitakami, Kazuteru Namba
    IEEE Access 10 116982-116986 2022年11月  査読有り最終著者
  • Takumi Aoyama, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo
    Proceedings - 2021 7th Asia-Pacific Conference on Synthetic Aperture Radar, APSAR 2021 2021年  
    We are conducting an experiment for Circularly Polarized Synthetic Aperture Radar (CP-SAR) using Unmanned Aerial Vehicle (UAV). Raw image data obtained by radar is processed by FPGA on UAV. The Range Doppler Algorithm (RDA) is used for our image processing. Currently, our image processing system uses the KC705 evaluation board with Kintex-7 FPGA, and it communicates with CP-SAR controller unit to perform image processing. This KC705 evaluation board is a multipurpose board and has parts that are not used in image processing. Therefore, we select the parts required for image processing and design a board for SAR image processing that is smaller and lighter than the KC705.
  • Yuta Yamamoto, Kazuteru Namba
    IEICE Trans. Inf. & Syst. E103-D(10) 2125-2132 2020年10月  査読有り
  • Kazuteru Namba
    IEICE Trans. Inf. & Syst. E103-D(4) 892-895 2020年4月  査読有り筆頭著者
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE Trans. Comput. 68(2) 301-306 2019年2月  査読有り筆頭著者
  • Yuta Yamamoto, Kazuteru Namba
    2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018 2019年1月4日  
    Due to VLSI downsizing and high integration, the incidence of soft error has increased. The soft error is a temporary event caused by striking of a-rays and high energy neutron radiation. Since the scale of VLSI has become smaller in recent development, it is necessary to consider the occurrence of not only single node upset (SNU) but also double node upset (DNU). The existing High-performance, Low-cost, and DNU Tolerant Latch design (HLDTL) does not completely tolerate DNU. This paper presents a DNU tolerant latch to solve this problem by adding some transistors to the HLDTL latch.
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE Trans. Comput. 67(10) 1525-1531 2018年10月  査読有り
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE Trans. Very Large Scale Integr. Syst. 26(2) 230-238 2018年2月  査読有り
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE TRANSACTIONS ON COMPUTERS 65(12) 3794-3801 2016年12月  査読有り
    Processing at the nanometric scales presents unique challenges that may require new computational paradigms such as approximate computing. In this paper a novel approach to memory protection using an unequal protection code (UEP) is proposed; this approach is in synergy with approximate (or inexact) computing. Multi-level burst error correcting UEP codes are analyzed. These codes improve over previously presented two-level burst error correcting UEP codes, because they utilize different conditions and criteria in the code partitions and decoder construction. An analysis by which multiple partitions can be selected to reduce the expected error magnitude, is provided. The area and power consumption of the parallel decoders closely depend on the desired code function. Simulation shows that the area and power consumption of the parallel error pattern generator are proportional to the partition length; the gate depth however is not strongly related to the partition length. The results of this manuscript confirm that the proposed multi-level burst error correcting UEP codes reduce the hardware overhead with no significant degradation in storage protection as potential storage application for approximate computing systems.
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE Transactions on Multi-Scale Computing Systems 2(4) 291-296 2016年10月1日  査読有り
    This paper presents new codes (and the related encoder/decoder scheme) to address the significant drawback of a phase change memory (PCM), namely that its write latency is significantly longer than the read latency. The proposed scheme improves over existing schemes by reducing the average write latency and the number of SET operations in a PCM. A new code, referred to as the write time speed-up (WTS) code is introduced WTS improves over existing schemes previously employed for this operation, i.e., the flip-N-write and the write-once-memory (WOM) code. In the proposed WTS code, multiple codewords correspond to every information word the codewords are selected to reduce the number of SET operations (each requiring a longer time than the RESET operation in a PCM). The proposed scheme targets a reduction in SET operations, by executing them only when required, i.e., so making the SET operations to occur irregularly with the write operations. Simulation results are provided using an embedded benchmark suite they show that the proposed scheme incurs in a shorter average write time than the flip-N-write scheme as well as the existing scheme with the WOM code when parallel data is provided. Encoding and decoding times for the proposed scheme are significantly shorter than the read and write latencies of a PCM. Moreover, the hardware overhead (in the area for LUT-based implementations) for the encoder and decoder of of WTS code is significantly smaller than the PCM system size, thus making the proposed design viable for implementation.
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE TRANSACTIONS ON COMPUTERS 65(6) 2005-2009 2016年6月  査読有り
    This manuscript proposes three classes of codes for error correction in a storage system in which the memory cells do not have the same number of levels, i.e., a multiscale storage. The proposed codes are single multiscale-symbol error correction (SMSEC) codes and are capable of correcting any errors occurring on a single memory cell, namely a column-deleted SMSEC code, an element-compacted SMSEC code and a product SMSEC code. In the proposed codes, the codewords are divided into two partitions, the elements on the first partition are over GF(2(b1)), while those on the remaining partition are over GF(2(b2)). This paper also gives guidelines for selection among the three SMSEC codes to meet the desired hardware overhead in the parallel decoder for realistic parameters of the partition pair, such as (b(1), b(2)) = (4,3), (4,2) and (3,2). Moreover it is shown that the best choice for a MSS system is the SMSEC code with the shortest check bit length; if the check bit lengths of at least two codes are equal, then the use of the element-compacted SMSEC code incurs in the smallest hardware overhead.
  • Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi
    IEEE TRANSACTIONS ON COMPUTERS 65(3) 781-790 2016年3月  査読有り
    This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. A soft error rate (SER) analysis is also pursued to confirm the findings of the critical charge-based analysis. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A novel memory scheme with the proposed NVSRAM cells is proposed for tolerating MBU; in this scheme, only the error detection circuitry is required, because error correction is provided by the non-volatile elements of the NVSRAM cells. Simulation results show that the proposed scheme is very efficient in terms of delay and number of transistors (as measure of complexity). Moreover, the very high critical charge of some of the proposed cell designs reduces the number of MBU appearing as errors at the outputs of the memory, thus further reducing the error detection hardware required by the proposed scheme. An extensive evaluation and comparison of different schemes are presented.
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 16(1) 30-37 2016年3月  査読有り
    This paper presents a novel construction scheme for nonbinary single-error correcting (SEC) codes that yields highspeed parallel decoding. The proposed scheme utilizes two methods, namely, Improved and Reordered; these methods can be also combined. Both of these methods reduce the number of 1's in the parity-check matrix (H-matrix) by reducing the 1's in every row vector. This results in a reduction in the gate depth in the syndrome generator, thus achieving a shorter delay time for parallel decoding. In the proposed Improved method, for a single b-bit byte (i.e., 2(b)-ary symbol) error correcting code, the submatrix of the H-matrix corresponding to every b-bit byte is multiplied with a regular matrix. The so-called improved submatrix is generated using a heuristic (greedy) algorithm. The proposed Reordered method selects the correct b-bit bytes for deletion when shortening is performed. Simulation results show that the proposed scheme accomplishes a faster parallel decoding time than existing schemes. Furthermore, the proposed scheme is applicable to any class of linear SEC codes, whereas existing schemes are applicable only to specific codes. Extensive simulation results are provided to substantiate the viability of the proposed codes for faster parallel decoding (albeit incurring for most cases in modest increases of area and power dissipation due to additional circuitry).
  • Wei Wei, Kazuteru Namba, Fabrizio Lombardi
    2016 INTERNATIONAL GREAT LAKES SYMPOSIUM ON VLSI (GLSVLSI) 125-128 2016年  査読有り
    A hybrid memory cell usually consists of a Static Random Access Memory (SRAM) and an embedded Dynamic Random Access Memory (eDRAM) cell; hybrid cells are particularly suitable for cache design. A novel hybrid cache memory scheme (that has also non-volatile elements) is initially proposed; this scheme is assessed through extensive simulation to show significant improvements in performance. Different design implementations of the hybrid cache are then proposed at architectural level and different features (such as the memory hit rate, the Instruction Per Cycle (IPC) access pattern and the memory cell access time) are also simulated at this level using benchmarks to show the advantages of the proposed scheme for use as an hybrid cache.
  • Ri Cui, Kazuteru Namba
    IPSJ Transactions on System LSI Design Methodology 9 30-36 2016年  査読有り
    This paper presents a novel calibration method for Delay Value Measurement Circuit (DVMC), a class of embedded time to digital converter (TDC), using a variable clock generator for accurate delay measurement. The proposed method uses a design for calibration as well as a variable clock generator. The design utilizes a delay time controllable (DTC) inverter. It also uses two OR-NAND gates which work as selectors we reconfigure the construction of the ring oscillator (RO) in DVMC when calibrating the DTC inverter. The proposed scheme accomplishes more accurate calibration compared to the traditional calibration which only uses the variable clock generator. For example, when using a variable clock generator with the resolution of 5.2 ps, the resolution of the proposed method is 0.58 ps while the traditional method is 5.2 ps.
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE TRANSACTIONS ON COMPUTERS 64(10) 2902-2911 2015年10月  査読有り
    Approximate (or inexact) computing is an attractive paradigm for digital processing at nanometric scales for applications in which imprecision in computation can be tolerated for improvements in other computational figures of merit, such as power consumption, circuit complexity and delay. The same principles of approximate computing are investigated in this manuscript for storage protection using an unequal protection code (UEP). In the proposed UEP code, the codeword is divided into two partitions; these partitions have different error protection functions. This paper presents a new class of two-level burst error correcting UEP codes and its parallel decoder. The proposed code is more efficient than an existing code in term of code rate, area and power consumption for the parallel decoder.
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE TRANSACTIONS ON COMPUTERS 64(7) 2092-2097 2015年7月  査読有り
    This manuscript proposes non-binary orthogonal Latin square (OLS) codes that are amenable to a multilevel phase change memory (PCM). This is based on the property that the proposed (n symbols, k symbols) t-symbol error correcting code uses the same H matrix as an (n bits, k bits) binary t-bit error correcting OLS code. The new codes are shown to have a shorter check bit length and better probability in encoding/decoding than conventional binary OLS codes. Extensive results are provided for assessment and comparison. The proposed codes are also shown to be always better than the matrix codes, i.e. independently of the metric and the parameters employed in the comparison.
  • Wei Wei, Kazuteru Namba, Fabrizio Lombardi
    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 20-22- 91-94 2015年5月20日  査読有り
    Memory design has radically changed in the last few years the emergence of new technologies has further improved performance and the traditional separation of storage levels between Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is not viable as in the past. Recently, the embedded DRAM (eDRAM) has been proposed for cache utilization to improve density while attempting to retain high performance operations this scheme is often referred as hybrid due to the utilization of different technologies in a memory. In this paper, a hybrid scheme is proposed by adding non-volatile features and related circuits to the SRAM/eDRAM an Oxide Resistive Random Access Memory (RRAM) is utilized as nonvolatile storage in the embedded memory circuit. Different memory cells are proposed in this manuscript they are evaluated with respect to circuit-level figures of merit as related to operational features (read, write, static noise margin, power delay product) as well as tolerance to event upsets (critical charge) and variations. Extensive simulation results using nanometric PTMs are provided. It is shown that the proposed designs offer substantial improvements over previous hybrid cells as well as a conventional NAND Flash memory cell.
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 15(1) 75-81 2015年3月  査読有り
    This paper presents a novel high-speed Reed-Solomon (RS) decoder. The proposed decoder corrects in parallel adjacent and single-symbol errors; moreover, it serially corrects multiple-symbol errors other than adjacent errors. Its operation is based on a novel scheme that extends an existing binary BCH decoder such that a nonbinary RS code can be targeted. The proposed scheme, however, differs from previous schemes in the algorithm and construction of the parallel decoder; the proposed decoder is efficient for multilevel memory systems such as those utilizing phase change memory devices. Simulation results show that the proposed scheme requires a significantly smaller area and lower power than a traditional fully parallelized RS decoder capable of correcting any double-symbol errors in parallel. Furthermore, it is also shown that it requires a smaller area than a parallel error correction scheme using a nonbinary double-error-correcting orthogonal Latin square code.
  • Kentaroh Katoh, Kazuteru Namba
    PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015) 425-429 2015年  査読有り
    This paper proposes a low area calibration technique for TDC using a variable clock generator for accurate on-line delay measurement. For proposed calibration, we choose a sensitizable path whose end point is connected to TDC. Next we sensitize the path multiple times using a variable clock generator to apply the time intervals to TDC one by one. The TDC measures the time intervals one by one. From the obtained measurement results we can estimate the effects of process variation and aging on measurement results of TDC, and thus we can get accurate on-line delay measurement result and accurate failure prediction. Because the technique does not require extra circuits, except the variable clock generator and the two 2-to-1 switches, the area cost of the proposed calibration is low. In addition, the proposed calibration technique can be applied to not only basic monotonic TDCs, but also TDCs of different architecture such as ring oscillator-based ones. Experimental results confirm that the error of calibration depends on the resolution of the used variable clock generator. Area overhead is 9.6 %, which is 169.6 % smaller than the conventional stochastic calibration.
  • Kentaroh Katoh, Kazuteru Namba
    SENSORS AND MATERIALS 27(10) 933-943 2015年  査読有り
    In this paper, we present a time-to-digital converter (TDC)-based maximum delay sensor (MDS) for on-line timing error detection in the logic block of very large scale integration (VLSI) circuits. The MDS captured the maximum propagation delay of the target end point for on-line timing error detection. Because the MDS was TDC-based, the resolution was high. In addition, the periodic on-line maximum delay capturing for on-line timing error detection using an MDS did not interrupt normal operation. Because the MDS was a small digital circuit, it could be easily inserted into the logic blocks of high-speed and low-power processors and systems-on-chip (SOCs). With LTSPICE simulation using 45 rim metal gate/high-K/strained-Si of the predictive technology model, the behavior of the proposed analyzer was confirmed. The results showed that the area overhead is 34.9% on average.
  • Wei Wei, Fabrizio Lombardi, Kazuteru Namba
    2015 IEEE 15TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) 1206-1209 2015年  査読有り
    Memory design has radically changed in the last few years; the emergence of new technologies has further improved performance and the traditional separation of storage levels between Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is not viable as in the past. Recently, the embedded DRAM (eDRAM) has been proposed for cache utilization to improve density while attempting to retain high performance operations; this scheme is often referred to as hybrid due to the utilization of different technologies in a memory. In this paper, a hybrid scheme is proposed by adding non-volatile features and related circuits to the SRAM/eDRAM; an Oxide Resistive Random Access Memory (RRAM) is utilized as non-volatile storage in the embedded memory circuit. Different memory cells are proposed in this manuscript; they are evaluated with respect to circuit-level figures of merit as related to operational features (read, write, static noise margin, power delay product) as well as tolerance to event upsets (critical charge and SER analysis) and variations. Extensive simulation results using nanometric PTMs are provided.
  • Wei Wei, Fabrizio Lombardi, Kazuteru Namba
    Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 69-74 2014年11月18日  査読有り
    This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A SER analysis of these cells is also pursued. An extensive evaluation and comparison of different schemes are presented.
  • Wenpo Zhang, Kazuteru Namba, Hideo Ito
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E97D(10) 2719-2729 2014年10月  査読有り
    With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02 similar to 47.74% with 6.33 similar to 12.35% of hardware overhead.
  • Wei Wei, Kazuteru Namba, Jie Han, Fabrizio Lombardi
    IEEE TRANSACTIONS ON NANOTECHNOLOGY 13(5) 905-916 2014年9月  査読有り
    Energy consumption is a major concern in nanoscale CMOS ICs; the power-OFF operational mode and low-voltage circuits have been proposed to alleviate energy dissipation. Static random access memories (SRAMs) are widely used in today's chips; nonvolatile SRAMs (NVSRAMs) have been proposed to preserve data, while providing fast power-ON/OFF speeds. Nonvolatile operation is usually accomplished by the use of a resistive RAM circuit (hence referred to as RRAM); the utilization of a RRAM with an SRAMs not only enables chips to achieve low energy consumption for nonvolatile operation, but it also permits to restore data when a restore on power-up is performed (this operation is also commonly referred to as "Instant-on"). This paper presents a novel NVSRAM circuit for "Instant-on" operation and evaluates its performance at nanometric feature sizes. The proposed memory cell consists of a SRAM core (in this case, a 6T cell) and an oxide resistive RRAM circuit (1T1R), thus making a 7T1R scheme. The proposed cell offers better nonvolatile performance (in terms of operations such as "Store," "Power-down," and "Restore") when compared with existing nonvolatile cells. The scenario of multiple-context configuration is also analyzed. Figures of merit such as energy, operational delay, and area are also substantially improved, making the proposed design a better scheme for "Instant-on" operation.
  • Kazuteru Namba, Salvatore Pontarelli, Marco Ottavi, Fabrizio Lombardi
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 14(2) 664-671 2014年6月  査読有り
    This paper presents a novel high-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than double-adjacent errors. Its operation is based on extending an existing parallel BCH decoder that can only correct single-bit errors and serially corrects double-adjacent errors at low speed. The proposed decoder is constructed by a novel design and is suitable for nanoscale memory systems, in which multiple-bit errors occur at a probability comparable to single-bit errors and double-adjacent errors occur at a higher probability (nearly two orders of magnitude) than other multiple-bit errors. Extensive simulation results are reported. Compared with the existing scheme, the area and delay time of the proposed decoder are on average 11% and 6% higher, but its power consumption is reduced by 9% on average. This paper also shows that the area, delay, and power overheads incurred by the proposed scheme are significantly lower than traditional fully parallelized BCH decoders capable of correcting any double-bit errors in parallel.
  • Wenpo Zhang, Kazuteru Namba, Hideo Ito
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E97D(3) 533-540 2014年3月  査読有り
    In recent VLSIs, small-delay defects, which are hard to detect by traditional delay fault testing, can bring about serious issues such as short lifetime. To detect small-delay defects, on-chip delay measurement which measures the delay time of paths in the circuit under test (CUT) was proposed. However, this approach incurs high test cost because it uses scan design, which brings about long test application time due to scan shift operation. Our solution is a test application time reduction method for testing using the on-chip path delay measurement. The testing with on-chip path delay measurement does not require capture operations, unlike the conventional delay testing. Specifically, FFs keep the transition pattern of the test pattern pair sensitizing a path under measurement (PUM) (denoted as p) even after the measurement of p. The proposed method uses this characteristic. The proposed method reduces scan shift time and test data volume using test pattern merging. Evaluation results on ISCAS89 benchmark circuits indicate that the proposed method reduces the test application time by 6.89 similar to 62.67% and test data volume by 46.39 similar to 74.86%.
  • Kazuteru Namba, Fabrizio Lombardi
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 14(1) 112-120 2014年3月  査読有り
    This paper presents a concurrent error detection (CED) scheme for orthogonal Latin square (OLS) parallel decoders. Different from a CED scheme found in the technical literature that protects only the syndrome generator, the proposed CED scheme protects the whole OLS decoder for single stuck-at faults. This paper presents the detailed design and analysis of the proposed CED scheme and shows that it is strongly fault secured for single stuck-at faults. Extensive simulation results are also provided; different figures of merit such as area, power dissipation, gate depth, and coverage are assessed. It is shown that the proposed decoder designs for (n, k) t-bit error correcting OLS codes (k = 16 ... 256; t = 2 ... 5) have reasonable overhead; for example, the average area overhead of the proposed CED is 35.5 (23.6) % compared with an OLS decoder with no CED (i.e., the previously reported CED scheme). However, the most significant advantage of the proposed scheme is that it achieves 100% fault coverage for the whole CED circuit, thus providing a very efficient and fully fault-tolerant implementation. The proposed CED is applicable to both binary and nonbinary OLS codes; the CED for a nonbinary OLS decoder achieves comparable or better results than a binary OLS decoder. Moreover, simulation shows that the proposed CED scheme is better than double modular redundancy.
  • Wei Wei, Kazuteru Namba, Fabrizio Lombardi
    GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI 199-204 2014年  査読有り
    Dynamic Random Access Memories (DRAM) are widely used in processor design. Different cells have been proposed in the past to overcome concerns associated with low retention time, degradation in performance due to process variations and susceptibility to soft errors. This paper proposes two novel DRAM cells (referred to as 4TI and 4T1D) that utilize the techniques of gated diode and forward body-biasing to overcome the above issues. The designs of these cells are evaluated by HSPICE simulation; different figures of merits (such as Read delay, Write delay, retention time, power dissipation, critical charge and layout area) are assessed and a comparative analysis of the proposed cells with existing cells is pursued. The 4TI cell achieves the best power dissipation, while the 4T1D achieves the best retention time, the highest critical charge and the least average Read delay. An extensive simulation based evaluation of process variations is also presented to confirm that using static and Monte Carlo based analysis, the proposed cells are likely to be less affected by process variations (in threshold voltage and effective channel length) than the other cells found in the technical literature.
  • Wenpo Zhang, Kazuteru Namba, Hideo Ito
    2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) 2014年  査読有り
    Recently, on-chip delay measurement was proposed to detect small-delay defects. However, small-delay defect coverage of on-chip delay measurement method is very low. A conventional method has been proposed to improve the small-delay defect coverage. However, it leads to high area overhead. To reduce the area overhead, this study presents a method using LOS+LOC based on the conventional method. To achieve a more effective defect coverage with the same hardware overhead, we should set the area of observation point occupies 50 similar to 70% of the overall hardware overhead. The proposed procedure can provide similar or higher defect coverage with very small hardware overhead. Specifically, the hardware overhead is 9.27 similar to 35.21% smaller than the conventional method.
  • Kazuteru Namba, Nobuhide Takashina, Hideo Ito
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E96D(8) 1613-1623 2013年8月  査読有り
    Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, In a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.
  • Kazuteru Namba, Takashi Katagiri, Hideo Ito
    Journal of Electronic Testing: Theory and Applications (JETTA) 29(4) 545-554 2013年8月  査読有り
    This paper presents a construction of timing-error-detecting dual-edge-triggered flip-flops (DET-FFs). The proposed FF is based on a conventional DET-FF and a conventional timing error detection method. While the conventional timing error detection uses a transition detector with relatively large area, the proposed FF uses internal signals in a DET-FF as as an alternative to the transition detector. This paper also shows an evaluation result indicating that the proposed FF has smaller area overhead than the simple combination of the conventional DET-FF and timing error detection methods. © 2013 Springer Science+Business Media New York.
  • Wenpo Zhang, Kazuteru Namba, Hideo Ito
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E96D(5) 1219-1222 2013年5月  査読有り
    As technology scales to 45 nm and below, the reliability of VLSI declines due to small delay defects, which are hard to detect by functional clock frequency. To detect small delay defects, a method which measures the delay time of path in circuit under test (CUT) was proposed. However, because a large number of FFs exist in recent VLSI, the probability that the resistive defect occurs in the FFs is increased. A test method measuring path delay time including the transmission time of FFs is necessary. However, the path measured by the conventional on-chip path delay time measurement method does not include a part of a master latch. Thus, testing using the conventional measurement method cannot detect defects occurring on the part. This paper proposes an improved on-chip path delay time measurement method. Test coverage is improved by measuring the path delay time including transmission time of a master latch. The proposed method uses a duty-cycle-modified clock signal. Evaluation results show that, the proposed method improves test coverage 5.25-11.28% with the same area overhead as the conventional method.
  • Kazuteru Namba, Fabrizio Lombardi
    Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 52-57 2013年  査読有り
    This paper presents a concurrent error detection (CED) scheme for Orthogonal Latin Square (OLS) parallel decoders. Different from a CED scheme found in the technical literature that protects only the syndrome generator, the proposed CED scheme protects the whole OLS decoder for single stuck-at faults. This paper presents the detailed design and analysis of the proposed CED scheme and shows that it is strongly fault secure (SFS) for single stuck-at faults. Extensive simulation results are also provided different figures of merit such as area, power dissipation, gate depth and coverage are assessed. It is shown that the proposed decoder designs for (n,k) t-bit error correcting OLS codes (k=16.256 t=2.5) have modest overheads. However, the most significant advantage of the proposed scheme is that it achieves 100 % fault coverage for the whole CED circuit, thus providing a very efficient and fully fault tolerant implementation. © 2013 IEEE.
  • Wenpo Zhang, Kazuteru Namba, Hideo Ito
    2013 IEEE INTERNATIONAL CONFERENCE OF IEEE REGION 10 (TENCON) 2013年  査読有り
    As IC design has entered into the nanometer scale integration and multi-gigahertz systems, small-delay defects which are hard to be detected by traditional delay fault testing, might become a reliability issue as the defect might magnify during subsequent aging in the field. Asynchronous design is used to solve some of the problems that appear when using global clocks on very large circuits. Small-delay defects in dual-rail asynchronous circuits affect the performance and lifetime of chips. Thus, small-delay defects are desired to be detected in manufacturing testing. This paper proposes a delay measurement to detect small-delay defects in 4-phase dual-rail asynchronous circuits. The proposed method is based on a traditional on-chip delay measurement using delay value measurement circuit (DVMC). The proposed method measures path delay time by adding a DVMC and some MUXes. Experimental results show that, by using the proposed method, we can detect small-delay defects in 4-phase dual-rail asynchronous circuits with a small hardware overhead. Specifically, the hardware overhead are 0.25 similar to 6.22% for some benchmark circuits.
  • Wei Wei, Kazuteru Namba, Fabrizio Lombardi
    IEEE Access 1 758-769 2013年  査読有り
    This paper deals with the design and evaluation of novel dynamic random access memory (DRAM) cells that have an oxide-based resistive element added for non-volatile operation. Two existing DRAM cells (namely the 3T1D and B3T cells) are utilized as volatile cores a RRAM circuitry (consisting of an access control transistor and an oxide resistive RAM) is added to the core to extend its operation for non-volatile operation two NVDRAM cells are then proposed. Considerations, such as the threshold voltage for the refresh operation and output read circuitry, are also considered. The impacts of the non- volatile circuitry as well as the DRAM core selection are assessed by HSPICE simulation. Figures of merit as related to performance, process variability, power consumption, and circuit design (critical charge and area of cell layout) are established for both volatile and non-volatile DRAM cells as well as memory arrays. © 2013 IEEE.
  • Kentaroh Katoh, Kazuteru Namba, Hideo Ito
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 20(5) 804-817 2012年5月  査読有り
    This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-mu m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.
  • Wenpo Zhang, Kazuteru Namba, Hideo Ito
    Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 193-198 2012年  査読有り
    In recent, with the nanometer-scale size, high density, and high frequency of VLSI, the reliability of VLSI is declined by the small-delay defects which are hard to be detected by traditional delay fault testing. As a method for detecting small-delay faults, on-chip delay measurement was proposed, which measures the delay time of paths on Circuit Under Test (CUT). However, if the Path Under Measurement (PUM) outputs a hazard, an incorrect stop signal will be generated. The incorrect stop signal can cause false error indications or test escapes. Therefore, when using on-chip measurement method to detect small-delay defects, single-path sensitization test pattern generation is required. Due to this constraint, the fault coverage is very low. This paper introduces techniques for improving fault coverage, which use multi-scan enable and test point insertion. Evaluation results indicate that for Launch On Shift (LOS) testing with single-path sensitization, by combination on these techniques, we can get an acceptable fault coverage. Specifically, fault coverage are improved 29.77-47.99% by 11.87-40.45% of hardware overhead. © 2012 IEEE.
  • Kazuteru Namba, Takashi Katagiri, Hideo Ito
    Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 187-192 2012年  査読有り
    This paper presents a construction of dual-edge-triggered flip-flops (DET-FFs) with timing error detection capability. The proposed FF is based on a conventional DET-FF and a conventional timing error detection method. While the conventional timing error detection uses a transition detector with the area of large, the proposed FF uses internal signals in a DET-FF as an alternative of the transition detector. This paper also shows an evaluation result indicating that the proposed FF has ten percent or smaller area overhead and lower power consumption than the simple combination of the conventional DET-FF and timing error detection methods. © 2012 IEEE.
  • Kazuteru Namba, Hideo Ito
    IEEE TRANSACTIONS ON COMPUTERS 60(10) 1459-1470 2011年10月  査読有り
    The significance of redundant technologies for improving dependability and delay fault testability are growing. So, delay fault testing on two-rail logic circuits well known as a class of redundant technologies will become important. Two-rail logic circuits can be efficiently tested by noncodeword vector pairs. However, noncodeword vector pairs may sensitize some faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with noncodeword vector pairs may be overtesting. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the overtesting. The amounts of test data for the proposed test sets are, on average, 28.2 percent less than those for the test sets, which are obtained by the existing construction for unate circuits and lead to the overtesting.
  • Kazuteru Namba, Hideo Ito
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E94D(5) 1045-1050 2011年5月  査読有り
    In this paper, a soft-error-tolerant BILBO (Built-In Logic Block Observer) FF (flip-flop) is presented. The proposed FF works as a soft-error-tolerant FP in system operations and as a BILBO FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft-error-tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF. The proposed FF contains a reconfigurable C-element with XNOR calculation capability, which works as a C-element for soft-error-tolerance during system operations and as an XNOR gate employed in linear feedback shift registers (LFSRs) during manufacturing testing. The evaluation results shown in this paper indicate that the area of the proposed FF is 8.5% smaller than that of a simple combination of the existing BISER and BILBO FFs. In addition, the sum of CLK-Q delay and D-CLK setup times on system operations for the proposed FF is 19.7% shorter than that for the combination.
  • Kiyonori Matsumoto, Kazuteru Namba, Hideo Ito
    IPSJ Transactions on System LSI Design Methodology 4 140-149 2011年  査読有り
    Scan architecture is one of designs for tests (DFTs). In scan architecture, some or all of flip-flops (FFs) in a circuit are serially connected and form a scan chain. The Chiba-scan is one of scan architectures facilitating delay testing. The Chiba-scan has many advantages such as small area overhead comparable to that of the standard scan architecture and complete fault coverage for robust testable path delay faults. However, its test volume is much larger than that of other scan architectures. This paper presents a test volume reduction method for robust path delay fault testing on the Chiba-scan. In this method, scan FFs are reordered. The experimental results give evidence that the proposed method reduces the number of test vectors by 18.4% for ISCAS89 benchmark circuits. Furthermore, the proposed method enables testing with 16.8% shorter test application time (TAT) and 18.3% lower required memory size for automatic test equipment (ATE) compared with those for the enhanced scan architecture. © 2011 Information Processing Society of Japan.
  • Kazuteru Namba, Kengo Nakashima, Hideo Ito
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E93D(12) 3407-3409 2010年12月  査読有り
    This paper presents a construction of a single event upset (SEU) tolerant reset set (RS) flip flop (FF) The proposed RS FF consists of four identical parts which form an interlocking feedback loop Just like DICE The area and average power consumption of the proposed RS FFs are 1 10 similar to 48 and 1 20 similar to 63 times smaller than those of the conventional SEU tolerant RS FFs respectively
  • Kazuteru Namba, Hideo Ito
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 26(6) 667-677 2010年12月  査読有り
    Delay fault testing using a scan design facilitating two-pattern testing, called Chiba scan testing, requires a long test application time (TAT) compared with well-known delay fault testing. This paper presents an improved Chiba scan testing with short TAT by providing a test compaction. In addition, it presents a test generation for the Chiba scan testing improved by the proposed compaction. Evaluation shows that, for robust path delay fault testing on ISCAS89/ ADDENDUM benchmark circuits, the TAT of Chiba scan testing with the proposed compaction is, on average, 47% and 21% shorter than that of Chiba scan testing without test compaction and that of enhanced scan testing with the conventional test compaction, respectively. In addition, in many cases, the fault coverage of the proposed testing is higher than that of launch-off-capture (LoC) and launch-off-shift (LoS) testing with the same TAT.
  • Kazuteru Namba, Takashi Ikeda, Hideo Ito
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18(9) 1265-1276 2010年9月  査読有り
    In recent high-density VLSIs, soft errors, particularly single event upsets (SEUs), frequently occur during system operation. In addition, the occurrence of delay faults caused by manufacturing defects is a significant problem. Thus, SEU tolerant design and delay fault testing are of increasing significance. This paper presents two types of SEU tolerant flip-flops (FFs). The proposed FFs tolerate SEUs caused by particles striking feedback loops in the FFs. Moreover, the proposed FFs allow enhanced scan delay fault testing. The proposed FFs are master-slave FFs, and the slave latches are constructed by modifying existing SEU tolerant latches, namely, SEH latches. The two proposed FFs tolerate particles with charges of 370 fC and of 369 fC or lower, whereas an existing SEU tolerant enhanced scan FF, called an ESFF-SEC, tolerates those of 431 fC or lower. Furthermore, the areas of the proposed FFs are 23.1% and 20.5% smaller than that of the ESFF-SEC. The CK-Q delay times are 44.4% and 41.1% shorter than that of the ESFF-SEC. Moreover, the average power consumptions of the proposed FFs during system operations are 55.6% and 53.3% lower than that of the ESFF-SEC.
  • 田辺 融, 加藤 健太郎, 難波 一輝, 伊藤 秀男
    信学論 D J93-D(4) 460-468 2010年4月  査読有り
  • Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito
    Proceedings - 16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010 229-230 2010年  査読有り
    Recently, the number of remote systems using the Internet has been increased and the services provided by such systems get various. They are required to have high dependability. The existing evaluations have some problems. For example, the evaluations based on RASIS are vague and those provided by Japanese government are very complicated. The existing evaluations are not uniformed, not understandable, and not quantitative. Especially, quantitative metric of integrity has not been proposed yet. This paper proposes quantitative metric for integrity for remote systems based on the Internet. It is also useful for evaluation of the effect of the measure against data destruction elements. This paper applies it to example systems in order to confirm its effectiveness. © 2010 IEEE.
  • Kazuteru Namba, Masatoshi Sakata, Hideo Ito
    2010 IEEE 25TH INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS (DFT 2010) 280-288 2010年  査読有り
    This paper presents a construction of a single-event-induced-double-node-upset-tolerant latch. The proposed latch does not tolerate upsets caused by single-and double-node-transients which single-events rarely induce because of single-event-transient occurrence mechanism. This paper also shows an evaluation result indicating the area of the proposed latch is only 0.44 times that of the conventional multiple-node-upset-tolerant latch, which tolerate any double-node-upsets and some limited triple-node-upsets, and is 1.01 times as large as that of the single-node-upset-tolerant latch DICE.

MISC

 41
  • SBIAI Takieddine, NAMBA Kazuteru, ITO Hideo
    電子情報通信学会技術研究報告 : 信学技報 111(324) 49-54 2011年11月28日  
    When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols...) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T^2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.
  • 大石 航志, 難波 一輝, 伊藤 秀男, スマンティヨ ヨサファット テトォコ スリ
    電子情報通信学会技術研究報告 : 信学技報 111(323) 37-41 2011年11月28日  
    我々のプロジェクトでは小型衛星において円偏波合成開口レーダ(CP-SAR)の運用を目指している.現在SAR画像処理は地上で行われているが,画像処理前のSAR画像は容量が大きいので,衛星や航空機等の飛行プラットフォーム上では記憶容量や通信時間の面で不利である.提案システムでは, SAR画像処理を飛行プラットフォーム上で行う.そのため,SAR画像の容量削減等の様々な効果を期待できる.この論文では,小型衛星運用前の準備実験である無人航空機(UAV)上で用いる予定のCP-SAR画像処理システムについて提案する.このシステムでは,データ容量が6,144 x 19,904 pixelsのSAR画像処理をViretx-6 FPGAと2GB DDR3 DRAMを搭載したXilinx ML605評価ボードで行う.
  • SBIAI Takieddine, NAMBA Kazuteru, ITO Hideo
    電子情報通信学会技術研究報告 : 信学技報 111(325) 49-54 2011年11月28日  
    When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols...) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T^2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.
  • 赤川 慎人, 難波 一輝, 伊藤 秀男
    電子情報通信学会技術研究報告 : 信学技報 111(325) 121-126 2011年11月28日  
    テスト容易化設計のうち近年増加している遅延故障の検出に対応した手法の1種にスキャン設計がある.このスキャン設計の1つとして千葉大スキャンが提案された.千葉大スキャンはスタンダードスキャンと同じくらいの面積オーバヘッドで実装でき,100%のロバストまたはノンロバストパス遅延故障検出率を実現した手法である.しかし,特殊なテスト手順を必要とするため,テストパターンが増加する問題点がある.さらに,その特殊なテスト手順のために,既存のテストデータ圧縮手法の圧縮率もスタンダードスキャン等の場合に比べ低くなる.そこで,本研究ではスキャンチェーンを再構成することで,既存テストデータ圧縮手法の千葉大スキャンに対する圧縮率を向上させる手法を提案する.本手法では,圧縮作業以前にスキャンチェーンを再構成することで圧縮効率を向上させている.これによりスキャンチェーンを再構成しなかった場合と比較して平均で29.5%の圧締率向上を得ている.
  • Takieddine Sbiai, Kazuteru Namba, Hideo Ito
    研究報告システムLSI設計技術（SLDM） 2011(9) 1-6 2011年11月21日  
    When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols…) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols…) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.
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