Soft Error Tolerant BILBO FF

Kazuteru Namba, Hideo Ito

2010 IEEE 25TH INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS (DFT 2010) 73-81 2010年査読有り

This paper presents a construction of a flip-flop (FF) that works as a soft error tolerant FF in system operations and as a BILBO (Built-In Logic Block Observer) FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft error tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF. The proposed FF contains a reconfigurable C-element with XNOR calculation capability, which works as a C-element for soft error tolerance during system operations and as an XNOR gate employed in linear feedback shift registers (LFSRs) during manufacturing testing. This paper also shows an evaluation result indicating the area of the proposed FF is 11.4% smaller than that of a simple combination of the existing BISER and BILBO FFs. In addition, the sum of CLK-Q delay and D-CLK setup times on system operations for the proposed FF is 34.8% shorter than that for the combination.
A Low Area On-Chip Delay Measurement System Using Embedded Delay Measurement Circuit

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010) 343-348 2010年査読有り

This paper presents a low area on-chip delay measurement system using an embedded delay measurement circuit. To reduce the area, the proposed method does not demand the measurement of the exact path under measurement, but the measurement of a path including the path under measurement and wires of clock tree unlike the conventional methods. The proposed Stop Signal Generator (SSG) consists of OR gate trees and a selector circuit. In addition, the area of SSG is lower than the conventional one. SSG is additional circuit which sends the transition from the output of the path under measurement to the embedded delay measurement circuit. Therefore, the area of the proposed system is lower. Because the area is low, the proposed method can be used for small-delay defect detection in manufacturing testing and failure prediction due to aging after shipment. We can apply the proposed delay measurement system to any embedded delay measurement circuit that measures the time difference between the two input signal transitions sent to the circuit. The evaluation shows that the area overhead is 16.54%. It is 6.62% smaller than the conventional method, and 8.41% larger than standard scan design.
A Low-Area and Short-Time Scan-Based Embedded Delay Measurement Using Signature Registers

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT) 311-314 2010年査読有り

This paper presents a low-area and short-time scan design for delay measurement using signature registers. The number of redundant latches is reduced utilizing X bits of test data for the delay measurement. After that, with the optimization of the scan chain routing, the scan chain length is reduced without decrease of the number of the measurable paths. These techniques keep the area overhead in the same order of that of the conventional scan designs for testing. In addition, the techniques further reduce the measurement time. Evaluation shows that the area overhead is 22.1% larger and 24.0% smaller than standard scan design and enhanced scan design respectively, which is in the order of scan designs for test. The measurement time is 90% shorter than that of standard scan design.
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits

Kazuteru Namba, Hideo Ito

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A(9) 2295-2303 2009年9月査読有り

The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults Occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for ally input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.
Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability

Shuangyu Ruan, Kazuteru Namba, Hideo Ito

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E92D(8) 1534-1541 2009年8月査読有り

In the recent high-density and low-power VLSIs, the occurrence of soft errors has become a significant problem. Recently, soft errors frequently occur on not only memory system but also logic circuits. Based on this standpoint, some constructions of soft-error-tolerant FFs were proposed. A conventional FF consists of some master and slave latches and C-elements. In the FF, soft error pulses occurring on combinational parts of logic circuits are corrected as long as the width of the pulses is narrow, that is within a specified width. However, error pulses with wide width are neither detected nor corrected in the FF. This paper presents a construction of soft-error-tolerant FFs by modifying the conventional soft-error-tolerant FF. The proposed FFs have the capability to detect error pulses having wide width as well as the capability to correct those having narrow width. The proposed FFs are also capable of detecting hard errors. The evaluation shows the soft-error-tolerant capability, AC characteristics, area overhead and power consumption of the FFs.
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E92D(3) 433-442 2009年3月査読有り

This paper proposes it scan design for delay fault testability of dual circuits. In normal operation mode, each proposed scan flip flop operates its it master-slave flip flop. In test nude. the proposed scan design performs scan operation Using two scan paths, namely master scan path and slave scan path. The master scan path consists of master latches and the slave scan path consists of slave latches. In the proposed scan design, arbitrary two-patterns can he set to flip flops of dual circuits. Therefore, it achieves complete fault coverage for robust and non-robust testable delay fault testing. It requires no extra latch unlike enhanced scan design. Thus the area overhead is low. The evaluation shows the test application time of the proposed scan design is 58.0% of that of the enhanced scan design. and the area overhead of the proposed scan design is 13.0% lower than that of the enhanced scan design. In addition, in testing of single circuits, it achieves complete fault coverage of robust and non-robust testable delay fault testing. It requires smaller test data volume than the enhanced scan design in testing of single circuits.
Design for Delay Fault Testability of 2-Rail Logic Circuits

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E92D(2) 336-341 2009年2月査読有り

This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.
Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding

Kazuteru Namba, Hideo Ito

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E92D(2) 269-282 2009年2月査読有り

This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding

Kazuteru Namba, Yoshikazu Matsui, Hideo Ito

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 25(1) 97-105 2009年2月査読有り

This paper proposes a class of test compression for IP (intellectual property) core testing. The proposed compression requires only test cubes for the IP cores and it dose not require the structural information about the IP cores. It uses both a reconfigurable network and classes of coding, namely fixing-flipping coding and fixing-shifting-flipping coding. The proposed compression is evaluated from the viewpoint of compression rates and hardware overhead. For three out of four large ISCAS89 benchmark circuits, the compression rates of the proposed compression are better than those of the four existing test compressions.
Testing of Switch Blocks in Three-Dimensional FPGA

Takumi Hoshi, Kazuteru Namba, Hideo Ito

IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE VLSI SYSTEMS, PROCEEDINGS 227-235 2009年査読有り

In recent years. programmable interconnects in Field Programmable Gate Arrays (FPGAs) become a bottleneck of improving performance. So, for improving performance of FPGAs, a design of programmable interconnects is a key element, and innovative routing architecture is being desired From this viewpoint, three dimensional FPGAS (3D-FPGAs) were proposed and focused. 3D-FPGAs have multiple layers which connected by vertical wires through 3D-Switch Block (SB). The main difference between the structures of the traditional two dimensional (2D) FPGAs and 3D-FPGAs is in 3D-SBs, and thus parts in 3D-FPGAs other than the SBs can be tested using existing methods for 2D-FPGAs. However, 3D-SBs cannot be tested by traditional testing for 2D-FPGAs. This paper presents testing for 3D-SBs in 3D-FPGAs. The proposed testing can detect stuck-at, bridging, stuck-open and stuck-on faults on three-dimensional switch blocks, and requires five test configurations to detect these catastrophic faults.
A Delay Measurement Technique Using Signature Registers

Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito

2009 ASIAN TEST SYMPOSIUM, PROCEEDINGS 157-162 2009年査読有り

This paper proposes a delay measurement technique using signature registers, and a scan design for delay measurement utilizing the proposed delay measurement technique to detect small-delay defects. The delay of circuits can be measured with the scan design with lower area.. smaller data volume and shorter measurement time than with the conventional scan design for delay measurement. Accordingly, the small-delay defects outside the range of the normal-distributed delay are detected with lower cost. Evaluation with 0.18 mu m process shows that the area overhead of the proposed scan design is 32.2 % smaller than that of the conventional method. The measurement time and the data volume for the measurement are reduced 66.7% and 66.0% compared with the conventional method, respectively.
Dependability Evaluation for Internet-based Remote Sysmtems

Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito

IEEE 15TH PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS 256-+ 2009年査読有り

Recently, the number of remote systems using the Internet has been increased and the services provided by such systems get various. They are required to have high dependability. The existing evaluations have some problems. For example, the evaluations based on RASIS are vague and those provided by Japanese government are very complicated. The existing evaluations are not uniformed, not understandable, and not quantitative. This paper proposes security evaluation metric which is a part of RASIS for remote systems using the Internet. The proposed metric gives quantitative evaluation in the similar manner of availability evaluation. It is based on the time that the system can tolerate take-over attack, which is one of the biggest threats among the attacks through the Internet. It can give appropriate system parameters to achieve the desired security. This paper applies it to example systems in order to confirm its effectiveness.
Two-stage stuck-at fault test data compression using scan flip-flops with delay fault testability

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IPSJ Transactions on System LSI Design Methodology 1 91-103 2008年8月査読有り

This paper presents a stuck-at fault test data compression using the scan flip flops with delay fault testability namely the Chiba scan flip-flops. The feature of the proposed method is two-stage test data compression. First, test data is compressed utilizing the structure of the Chiba scan flip flops (the first stage compression). Second, the compressed test data is further compressed by conventional test data compression utilizing X bits (the second stage compression). Evaluation shows that when Huffman test data compression is used in the second stage compression, the volume of test data for the proposed test data compression in ATE is reduced 35.8% in maximum, 25.7% on average of the one of the test data compressed by the conventional method. The difference of the area overhead of the proposed method from the conventional method is 9.5 percent point. © 2008 Information Processing Society of Japan.
Circuit and latch capable of masking soft errors with schmitt trigger

Yoichi Sasaki, Kazuteru Namba, Hideo Ito

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 24(1-3) 11-19 2008年6月査読有り

In VLSIs, soft errors resulting from radiation-induced transient pulses frequently occur. In recent high-density and low-power VLSIs, the operation of systems is seriously affected by not only soft errors occurring on memory systems and the latches of logic circuits but also those occurring on the combinational parts of logic circuits. The existing tolerant methods for soft errors on the combinational parts do not provide enough high tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and a pass transistor. The paper also presents a construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, simulation results show that the proposed method has higher soft error tolerant capability than the existing methods. For supply voltage V-DD= 3.3 V, the proposed method is capable of masking transient pulses of magnitude 4.0 V or less.
Path delay fault test set for two-rail logic circuits

Kazuteru Namba, Hideo Ito

Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008 347-348 2008年査読有り

Two-rail logic circuits can be efficiently tested by non-codeword vector pairs. However, non-codeword vector pairs may sensitize some path delay faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with non-codeword vector pairs may be over-testing. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the over-testing. © 2008 IEEE.
Soft Error Hardened FF Capable of Detecting Wide Error Pulse

Shuangyu Ruan, Kazuteru Namba, Hideo Ito

23RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS 272-280 2008年査読有り

In the recent high-density and low-power VLSIs occurrence of soft errors becomes significant problems Recently, soft errors frequently occur on not only memory system but also circuits. Based on this standpoint, constructions of soft error tolerant FTs have been proposed. The FTs consist of some master and slave latches and C-elements. In the FTs, soft error pulses occurring oil combinational parts of logic circuits are corrected as long as the width of the pulses is narrow that is within a specified width. However soft error pulses or other error pulses having wide width are neither detected nor corrected in the FTs. This paper presents a construction of another soft error tolerant FTs being added some latches and delay elements into the conventional soft error tolerant FTs. The proposed FFs have capability detecting error pulses having wide width as well as capability correcting those having narrow width. The proposed FFs are also capable of detecting hard errors. This paper also presents scan FFs facilitating delay fault testing and soft error tolerant FFs for two-rail logic circuit based on the proposed FTs, The evaluation shows that the area of the proposed FF is up to 66% larger than that of the conventional soft error tolerant FTs.
Delay Fault Testability on Two-Rail Logic Circuits

Kazuteru Namba, Hideo Ito

23RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS 482-490 2008年査読有り

The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant techologies, namely two-rail logic, and discusses testability of path delay faults occuring oil two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is just twice that in ordinary single-rail logic circuits. the number of robust testable path delay faults in two-rail logic circuits is twice at, more that in the single-rail logic circuits This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, path delay faults arc always functional senzitable and may be robust testable. Even if faults that no codeword input vectors functionally sensitize occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.
Soft error hardened latch scheme for enhanced scan based delay fault testing

Takashi Ikedai, Kazuteru Namba, Hideo Ito

DFT 2007: 22ND IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS 282-290 2007年査読有り

In recent high-density, high-speed and low-power VLSIs, soft errors (M) and delay faults (DFs) frequently occur. Therefore, SE hardened design and DF testing are essential. This paper proposes three types of scan flip-flops (FFs) which have SE tolerant capability and allow enhanced scan shifting for DF testing, i.e. arbitraty two-pattern testing. The slave latches used in these FFs are constructed by adding some extra transistors which make enhanced scan shifting possible fir DF testing on an existing SE hardened latch. The areas and time overheads of the proposed latches are tip to 33.3% and 31.4% larger than those of the existing SE hardened latch respectively. However, the areas of the proposed FFs are about 30% smaller than existing FFs which have SE tolerant capability and allow enhanced scan shifting for DF testing.
Redundant design for Wallace multiplier

Kazuteru Namba, Hideo Ito

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E89D(9) 2512-2524 2006年9月査読有り

To increase the yield of data processing circuits such as adders and logic operation circuits, the bit-slice reconfiguration design has been proposed as an efficient redundant technology for defect-tolerance. Wallace multipliers are a well-known class of high-speed parallel multipliers. Unfortunately, the bit-slice reconfiguration design is not applicable to Wallace multipliers because Wallace multipliers do not have regular bit-slice structure. Therefore, redundant designs for Wallace multipliers have been regarded impossible. This paper proposes a redundant design for Wallace multipliers. In order to design redundant Wallace multipliers, first, 2n heterogeneous slices are considered in a non-redundant n x n Wallace multiplier. The proposed redundant Wallace multipliers contain reconfigurable slices which can play the role of both i-th and (i + 1)-th slices. Since the i-th slice has a similar structure to the (i + 1)-th slice, the reconfigurable slice is not much larger than the i-th slice. This paper also shows a repair procedure for the proposed design. This paper evaluates the proposed design from the viewpoint of the yield, area, effective yield and delay time. For example, the yield of a 32 x 32 Wallace multiplier increases from 0.30 to 0.41 by applying the proposed design while the area increases by a factor of 1.21.
Proposal of testable multi-context FPGA architecture

Kazuteru Namba, Hideo Ito

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E89D(5) 1687-1693 2006年5月査読有り

Multi-context FPGAs allow very quick reconfiguration by storing multiple configuration data at the same time. While testing for FPGAs with single-context memories has already been studied by many researchers, testing for multi-context FPGAs has not been proposed yet. This paper presents an architecture of testable multi-context FPGAs. In the proposed multi-context FPGA, configuration data stored in a context can be copied into another context. This paper also shows testing of the proposed multi-context FPGA. The proposed testing uses the testing for the traditional FPGAs with single-context. The testing is capable of detecting single stuck-at faults and single open faults which affect normal operations. The number of test configurations for the proposed testing is at most two more than that for the testing of FPGAs with single-context memories. The area overhead of the proposed architecture is 7% and 4% of the area of a multi-context FPGA without the proposed architecture when the number of contexts in a configuration memory is 8 and 16, respectively.
Soft error masking circuit and latch using Schmitt trigger circuit

Yoichi Sasaki, Kazuteru Namba, Hideo Ito

21ST IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS 327-+ 2006年査読有り

In recent high-density and low-power VLSIs, soft errors occurring on not only memory systems and the latches of logic circuits but also the combinational parts of logic circuits seriously affect the operation of systems. The conventional soft error tolerant methods for soft errors on the combinational parts do not provide enough high soft error tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and pass transistors. The paper also presents construction Of soft error masking latches (SEM-Latches) capable of masking transient pulses occurring on combinational circuits. Moreover, experimental results show that the proposed method has higher soft error tolerant capability than the existing methods. For driving voltage VDD =3.3 V, the proposed method is capable of masking transient pulses of magnitude 4.0 V or less.
Interleaving of delay fault test data for efficient test compression with statistical coding

Kazuteru Namba, Hideo Ito

PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM 389-+ 2006年査読有り

This paper proposes a method providing efficient test compression, for delay fault testing using enhanced scan design. In the proposed method, the initial anal transition. vectors of test data are interleaved before test compression using statistical coding. This paper also shows test architecture for delay fault testing using the proposed method. The proposed method is experimentally evaluated from the viewpoint of compression rates. For robust. testable path. delay fault testing on, 11 out of 23 ISCAS89 benchmark circuits, the combination of Huffman coding anal the proposed method provides higher compression rates than. Huffman. coding without the proposed method, run-length. coding, Golomb coding; frequency-directed run-length (FDR) coding and variable-length. input Huffman coding (VIHC).
Scan design for two-pattern test without extra latches

K Namba, H Ito

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E88D(12) 2777-2785 2005年12月査読有り

There are three well-known approaches to using scan design to apply two-pattern testing: broadside testing (functional justification), skewed-load testing and enhanced scan testing. The broadside and skewed-load testing use the standard scan design, and thus the area overheads are not high. However fault coverage is low. The enhanced scan testing uses the enhanced scan design. The design uses extra latches, and allows scan-in any two-pattern testing. While this method achieves high fault coverage, it causes high area overhead because of extra latches. This paper presents a new scan design where two-pattern testing with high fault coverage can be performed with area overhead as low as the standard scan design. The proposed scan-FFs are based on master-slave FFs. The input of each scan-FF is connected to the output of the master latch and not the slave latch of the previous FF. Every scan-FF maintains the output value during scan-shift operations.
Deterministic delay fault BIST using adjacency test pattern generation

K Namba, H Ito

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E88D(9) 2135-2142 2005年9月査読有り

In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot generate test patterns for circuits with more than 30 inputs with high fault coverage in a practical amount of time. This paper proposes a deterministic delay fault BIST method using adjacency test pattern generation. The proposed scheme uses first patterns generated by a deterministic algorithm based on the analysis of independent partial circuits on the circuit under test. Experiments show that test patterns generated by the proposed method have both high fault coverage and short test length, resulting in a short test time.
Design of defect tolerant Wallace multiplier

K Namba, H Ito

11TH PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS 300-304 2005年査読有り

This paper proposes a design of a defect tolerant Wallace multipliers. A repair procedure for the proposed design is also shown. This paper evaluates the proposed design from the view point of the yield, area and delay time. For example, the yield of a 32 x 32 Wallace multiplier increases from 0.90 to 0.99 by applying the proposed design while the area increases by a factor of 1.39.
整数環上で構成した多元1シンボル誤り訂正・隣接2シンボル入れ換え誤り訂正符号

難波一輝, 藤原英二

信学論 D-I J86-D-I(1) 23-28 2003年1月査読有り
バースト誤り制御符号に対する並列復号法

藤原英二, 難波一輝, 北神正人

信学論 A J85-A(11) 1284-1295 2002年11月査読有り
Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities

Kazuteru Namba, Eiji Fujiwara

IEICE Trans. Fundamentals E85-A(6) 1426-1430 2002年6月査読有り
多元単一シンボル誤り訂正符号

難波一輝, 藤原英二

信学論 D-I J83-D-I(3) 368-374 2000年3月査読有り

MISC

A Dynamically Configurable NoC Test Access Mechanism (VLSI設計技術)

SBIAI Takieddine, NAMBA Kazuteru, ITO Hideo

電子情報通信学会技術研究報告 : 信学技報 111(324) 49-54 2011年11月28日

When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols...) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T^2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.
2枚のFPGAボードとPCを使用したUAV搭載CP-SAR画像処理システム (リコンフィギャラブルシステム)

大石航志, 難波一輝, 伊藤秀男, スマンティヨヨサファットテトォコスリ

電子情報通信学会技術研究報告 : 信学技報 111(323) 37-41 2011年11月28日

我々のプロジェクトでは小型衛星において円偏波合成開口レーダ(CP-SAR)の運用を目指している.現在SAR画像処理は地上で行われているが,画像処理前のSAR画像は容量が大きいので,衛星や航空機等の飛行プラットフォーム上では記憶容量や通信時間の面で不利である.提案システムでは, SAR画像処理を飛行プラットフォーム上で行う.そのため,SAR画像の容量削減等の様々な効果を期待できる.この論文では,小型衛星運用前の準備実験である無人航空機(UAV)上で用いる予定のCP-SAR画像処理システムについて提案する.このシステムでは,データ容量が6,144 x 19,904 pixelsのSAR画像処理をViretx-6 FPGAと2GB DDR3 DRAMを搭載したXilinx ML605評価ボードで行う.
A Dynamically Configurable NoC Test Access Mechanism (ディペンダブルコンピューティング)

SBIAI Takieddine, NAMBA Kazuteru, ITO Hideo

電子情報通信学会技術研究報告 : 信学技報 111(325) 49-54 2011年11月28日

When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols...) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T^2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.
スキャンチェーンの再構成による千葉大スキャンテストデータ圧縮率向上手法 (ディペンダブルコンピューティング)

赤川慎人, 難波一輝, 伊藤秀男

電子情報通信学会技術研究報告 : 信学技報 111(325) 121-126 2011年11月28日

テスト容易化設計のうち近年増加している遅延故障の検出に対応した手法の1種にスキャン設計がある.このスキャン設計の1つとして千葉大スキャンが提案された.千葉大スキャンはスタンダードスキャンと同じくらいの面積オーバヘッドで実装でき,100%のロバストまたはノンロバストパス遅延故障検出率を実現した手法である.しかし,特殊なテスト手順を必要とするため,テストパターンが増加する問題点がある.さらに,その特殊なテスト手順のために,既存のテストデータ圧縮手法の圧縮率もスタンダードスキャン等の場合に比べ低くなる.そこで,本研究ではスキャンチェーンを再構成することで,既存テストデータ圧縮手法の千葉大スキャンに対する圧縮率を向上させる手法を提案する.本手法では,圧縮作業以前にスキャンチェーンを再構成することで圧縮効率を向上させている.これによりスキャンチェーンを再構成しなかった場合と比較して平均で29.5%の圧締率向上を得ている.
A Dynamically Configurable NoC Test Access Mechanism

Takieddine Sbiai, Kazuteru Namba, Hideo Ito

研究報告システムLSI設計技術（SLDM） 2011(9) 1-6 2011年11月21日

When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols…) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols…) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.

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