難波 一輝

When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols...) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T^2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.

我々のプロジェクトでは小型衛星において円偏波合成開口レーダ(CP-SAR)の運用を目指している.現在SAR画像処理は地上で行われているが,画像処理前のSAR画像は容量が大きいので,衛星や航空機等の飛行プラットフォーム上では記憶容量や通信時間の面で不利である.提案システムでは, SAR画像処理を飛行プラットフォーム上で行う.そのため,SAR画像の容量削減等の様々な効果を期待できる.この論文では,小型衛星運用前の準備実験である無人航空機(UAV)上で用いる予定のCP-SAR画像処理システムについて提案する.このシステムでは,データ容量が6,144 x 19,904 pixelsのSAR画像処理をViretx-6 FPGAと2GB DDR3 DRAMを搭載したXilinx ML605評価ボードで行う.

When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols...) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T^2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.

テスト容易化設計のうち近年増加している遅延故障の検出に対応した手法の1種にスキャン設計がある.このスキャン設計の1つとして千葉大スキャンが提案された.千葉大スキャンはスタンダードスキャンと同じくらいの面積オーバヘッドで実装でき,100%のロバストまたはノンロバストパス遅延故障検出率を実現した手法である.しかし,特殊なテスト手順を必要とするため,テストパターンが増加する問題点がある.さらに,その特殊なテスト手順のために,既存のテストデータ圧縮手法の圧縮率もスタンダードスキャン等の場合に比べ低くなる.そこで,本研究ではスキャンチェーンを再構成することで,既存テストデータ圧縮手法の千葉大スキャンに対する圧縮率を向上させる手法を提案する.本手法では,圧縮作業以前にスキャンチェーンを再構成することで圧縮効率を向上させている.これによりスキャンチェーンを再構成しなかった場合と比較して平均で29.5%の圧締率向上を得ている.

When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols…) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on NoC reusing as TAM, in which, communication infrastructure of the NoC (routers, interconnection links, protocols…) is reused as TAM. While NoC reuse as TAM can achieve a low area overhead, test scheduling is a difficult issue, due to the fact that test data are exchanged in packets. Based on this drawback, this paper presents a new method which consists of reconfiguring the NoC hardware dynamically to act as a TAM. This configurability allows us to have the granularity of the traditional TAM which facilitates test scheduling, and the advantages of the NoC communication infrastructure, which give us the possibility of parallel testing, low area overhead and usage of the functional NoC frequencies. The proposed TAM is then compared to a conventional NoC reuse as TAM methods and a TAM architecture named T2-TAM using two ITC'02 benchmark circuits. The presented results show a test time reduction between 17% and 55% while imposing a 9.6% area overhead.