Wei Wei   Kazuteru Namba   Yong-Bin Kim   Fabrizio Lombardi   
IEEE TRANSACTIONS ON COMPUTERS 65(3) 781-790 2016年3月 [査読有り]
This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at ...
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 16(1) 30-37 2016年3月 [査読有り]
This paper presents a novel construction scheme for nonbinary single-error correcting (SEC) codes that yields highspeed parallel decoding. The proposed scheme utilizes two methods, namely, Improved and Reordered; these methods can be also combined...
2016 INTERNATIONAL GREAT LAKES SYMPOSIUM ON VLSI (GLSVLSI) 125-128 2016年 [査読有り]
A hybrid memory cell usually consists of a Static Random Access Memory (SRAM) and an embedded Dynamic Random Access Memory (eDRAM) cell; hybrid cells are particularly suitable for cache design. A novel hybrid cache memory scheme (that has also non...
IPSJ Transactions on System LSI Design Methodology 9 30-36 2016年 [査読有り]
This paper presents a novel calibration method for Delay Value Measurement Circuit (DVMC), a class of embedded time to digital converter (TDC), using a variable clock generator for accurate delay measurement. The proposed method uses a design for ...
IEEE TRANSACTIONS ON COMPUTERS 64(10) 2902-2911 2015年10月 [査読有り]
Approximate (or inexact) computing is an attractive paradigm for digital processing at nanometric scales for applications in which imprecision in computation can be tolerated for improvements in other computational figures of merit, such as power ...
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on No...
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on No...
Takieddine Sbiai   Kazuteru Namba   Hideo Ito   
研究報告システムLSI設計技術(SLDM) 2011(9) 1-6 2011年11月
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on No...