IEEE TRANSACTIONS ON COMPUTERS 64(7) 2092-2097 2015年7月 [査読有り]
This manuscript proposes non-binary orthogonal Latin square (OLS) codes that are amenable to a multilevel phase change memory (PCM). This is based on the property that the proposed (n symbols, k symbols) t-symbol error correcting code uses the sam...
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 20-22- 91-94 2015年5月 [査読有り]
Memory design has radically changed in the last few years
the emergence of new technologies has further improved performance and the traditional separation of storage levels between Static Random Access Memory (SRAM) and Dynamic Random Access Mem...
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 15(1) 75-81 2015年3月 [査読有り]
This paper presents a novel high-speed Reed-Solomon (RS) decoder. The proposed decoder corrects in parallel adjacent and single-symbol errors; moreover, it serially corrects multiple-symbol errors other than adjacent errors. Its operation is based...
PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015) 425-429 2015年 [査読有り]
This paper proposes a low area calibration technique for TDC using a variable clock generator for accurate on-line delay measurement. For proposed calibration, we choose a sensitizable path whose end point is connected to TDC. Next we sensitize th...
In this paper, we present a time-to-digital converter (TDC)-based maximum delay sensor (MDS) for on-line timing error detection in the logic block of very large scale integration (VLSI) circuits. The MDS captured the maximum propagation delay of t...
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on No...
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on No...
Takieddine Sbiai   Kazuteru Namba   Hideo Ito   
研究報告システムLSI設計技術(SLDM) 2011(9) 1-6 2011年11月
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on No...