2015 IEEE 15TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) 1206-1209 2015年 [査読有り]
Memory design has radically changed in the last few years; the emergence of new technologies has further improved performance and the traditional separation of storage levels between Static Random Access Memory (SRAM) and Dynamic Random Access Mem...
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 69-74 2014年11月 [査読有り]
This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed
these designs increase the cri...
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E97D(10) 2719-2729 2014年10月 [査読有り]
With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which ...
IEEE TRANSACTIONS ON NANOTECHNOLOGY 13(5) 905-916 2014年9月 [査読有り]
Energy consumption is a major concern in nanoscale CMOS ICs; the power-OFF operational mode and low-voltage circuits have been proposed to alleviate energy dissipation. Static random access memories (SRAMs) are widely used in today's chips; nonvol...
Kazuteru Namba Salvatore Pontarelli Marco Ottavi Fabrizio Lombardi
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 14(2) 664-671 2014年6月 [査読有り]
This paper presents a novel high-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than double-adjacent errors. Its operation is based on extending an existing paralle...
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on No...
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on No...
When designing a system on chip (SoC), a test access mechanism (TAM) is required to deliver test data and to collect test responses from cores under test (CUT). To facilitate the network on chip (NoC) testing, test engineers frequently focus on No...
大学院国際学術研究院